Electronic systems that use a high level of data bandwidth, such as in multimedia applications, may need memory devices that provide the necessary rate of data transfer and other advantages. One technology that may provide the necessary bandwidth is the Rambus technology marketed by Rambus, Inc. of Mountain View, Calif. The Rambus technology is described in U.S. Pat. No. 5,473,575 to Farmwald et al., U.S. Pat. No. 5,578,940 to Dillion et al., U.S. Pat. No. 5,606,717 to Farmwald et al. and U.S. Pat. No. 5,663,661 to Dillion et al. A device embodying the Rambus technology is an example of a packet type integrated circuit memory device, because each integrated circuit receives data and addresses in packet units in a normal mode of operation. The packet is received by the Rambus device which generates internal control signals, internal data signals, and internal address signals to carry out the corresponding operation of the packet. For example, the packet may include data, address, and control signals for a write operation.
FIG. 1 is a block diagram of a layout of internal circuits in a conventional Rambus integrated circuit memory device. As shown in FIG. 1, a conventional Rambus integrated circuit memory device 101 includes first and second memory banks 111 and 121, first and second core interfaces 113 and 123, first and second data shift blocks 131 and 141, interface logic block 151, first and second input/output units 161 and 162, a delay locked loop 163 and a pad block 171 that are arranged in an integrated circuit substrate.
As also shown in FIG. 1, the first core interface 113; the first data shift block 131; the interface logic 151; the combination of the first input/output unit 161, the delay locked loop 163 and the second input/output unit 162; the pad block 171; the second data shift block 141; and the second core interface 123 are serially arranged in the integrated circuit substrate along a first direction between the first and second memory banks 111 and 121. The first and second memory banks are selected by a bank selection signal BS.
A power supply voltage and a ground voltage are supplied to the first and second data shift blocks 131 and 141 via the pad block 171 from external of the integrated circuit memory device 101. Unfortunately, since the first data shift block 131 is remote from the pad block 171, the supply voltage and ground voltage that are supplied to the first data shift block may be prone to noise.
The delay locked loop 163 is responsive to an external clock signal CLK that is received from the pad block 171 to generate an internal clock signal SCLK. The delay locked loop provides the internal clock signal SCLK to the first and second data shift blocks 131 and 141 and to the interface logic block 151.
The interface logic block 151 is responsive to the internal clock signal to control the first and second memory banks 111 and 121 and the input/output units 161 and 162 in response to the internal clock signal.
The first data shift block 131 is connected between the first and second input/output units 161 and 162 and the first memory bank 111. The second data shift block 141 is connected between the first and second input/output units 161 and 162 and the second memory bank 121. The first and second data shift blocks 131 and 141 convert serial data from the input/output portions 161 and 162 into parallel data that is provided to the associated memory bank 111 or 121 and also convert parallel data that is received from the associated memory bank 111 or 121 into serial data that is provided to the first and second input/output units 161 and 162, respectively. Accordingly, the two data shift blocks 131 and 141 can facilitate signal connection to the internal circuits that are included in the Rambus integrated circuit memory device 101.
As packet type integrated circuit memory devices continue to be used in data processing systems, it is desirable to reduce the size of the packet type integrated circuit memory device. Moreover, it is also desirable to decrease the power consumption of the device and increase the performance thereof.